EEPROM (Electrically Erasable Programmable Read Only Memory) cells are a class of nonvolatile semiconductor memory in which information may be electrically programmed into and erased from each memory element or cell. Floating gate EEPROM cells are one type of EEPROM cell in which information is stored by placing electronic charge on a “floating gate”, typically a region of conductive polysilicon that is electrically isolated from other conducting regions of the device by insulating dielectric layers that surround it. The charge on the floating gate can be detected in reading the memory cell because it changes the threshold voltage of the memory transistor. This change in threshold voltage changes the amount of current that flows through the cell when voltages are applied to it during the read operation and the current can be detected by a sense amplifier circuit.
As stated above, EEPROM cells are nonvolatile, which means that they must retain their information (charge state) even when the power supplied to them is turned off. Thus, it is critically important that the charge stored on the floating gate not “leak” off over time. A product containing EEPROM cells usually has a retention specification in its data sheets which states how long the EEPROM memory cells will retain the information programmed into them without error when the power supplied to them is turned off. The dielectric isolation surrounding the floating gate must have very good integrity and this integrity must exist with respect to all of the cells in the memory device.
The charge on the floating gate is typically controlled by a “control gate,” which may be isolated from the floating gate by a 3-layer stack of dielectrics referred to as the “ONO”, which consists of a bottom layer of silicon dioxide, a middle layer of silicon nitride (Si3N4), and top layer of silicon dioxide, wherein the ONO provides a dielectric isolation between the floating and control gates.
The sidewall of the floating gate is typically sealed to prevent the leakage of charge (voltage) from the floating gate. This seal is commonly provided by a thermal poly-oxide formed on the floating gate sidewall, referred to herein as the “sidewall oxide.” The sidewall oxide may be defined by a vertical portion of a stacked oxide layer. FIG. 1 shows a partial cross-sectional representation of a conventional EEPROM cell, showing a conductive floating gate 28 formed over a silicon substrate 16, and separated from the silicon substrate 16 by a gate or tunnel oxide 42. A dielectric or ONO layer 32, including a silicon nitride (Si3N4) layer 108 between a pair of oxide layers, is formed on top of the floating gate 28, and a control gate (not shown in FIG. 1) may be formed over the ONO and underlying floating gate 28.
A sidewall oxide 114 may be formed over a side surface or wall 40 of the floating gate 28, for inhibiting voltage leakage from the floating gate 28. The sidewall oxide 114 may form a portion of a contiguous oxide layer extending above the ONO layer 32 and/or onto an upper surface of the substrate adjacent the floating gate 28, depending on the particular design. Different techniques have been used to form the sidewall oxide 114, which suffer from various drawbacks. For example, the process of forming the sidewall oxide may result in the unwanted growth of oxide under the floating gate 28, which may reduce the effective area of the gate oxide 42, and/or unwanted oxide growth of oxide underneath the ONO dielectric (e.g., by oxidation of the top surface of the floating gate 28), thereby effectively thickening the ONO and decreasing the coupling capacitance of the cell. As another example, some processes for forming the sidewall oxide may produce a non-uniform, e.g., outwardly bulging, shape of the sidewall oxide, and/or may result in sharp corners of the polysilicon control gate, both of which are generally undesirable.
FIG. 2 illustrates an image of an example EEPROM structure exhibiting the undesirable features discussed above. In this example the sidewall oxide was formed by a two-step process of depositing a thin high temperature oxide (HTO) film, followed by a furnace oxidation anneal. As shown, the resulting structure exhibits (a) undesirable oxide lateral encroachment into the ONO region, as indicated at regions A, (b) undesirable oxide encroachment under the floating gate, as indicated at regions B, resulting in an increase in the effective tunnel oxide thickness and a decrease in the tunneling channel area, (c) undesirably sharp corners of the Poly 2 layer (control gate), as indicated at C, and (d) a non-uniform thickness of the sidewall oxide, in particular defining an outward bulge, as indicated at D.